Clocking system

ABSTRACT

A ring counter having a one count delay during each cycle is used to clock a Johnson counter during the one count delay. A number of individually identifiable clock pulses are then available for clocking and sequential control functions by ANDing any one of the outputs of the ring counter with any one of the outputs of the Johnson counter, the total number being equal to the product of the number of ring counter outputs and the number of Johnson counter outputs.

United States Patent 3,230,352 1/1966 Grondinetal...... 3,420,990 1/1969AndreaetaL.

[72] Inventor Granville E. Ott

Houston, Tex.

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Dallas, Tex.

Hassell, Samuel M. Mims, .lr., ReneE. Grossman, Richards, Harris andHubbard and V. Bryan Medlock, Jr.

[54] CLOCKING SYSTEM 2 Claims, 5 Drawing Figs.

ABSTRACT: A ring counter havin each cycle is used to clock a John countdelay. A number of individual] ses are then available for clockin tionsby ANDing any one of th with any one of the outputs of the J numberbeing equal to the produ 2 82 2 2 wow w 5y 5 5 3 23 3 2m 2 2 63 0O GU mS m m m T. m H n N u m m m m m m M m m m P m n C n u SE e n u u C n. M.n e 0 u" Td N ms m mm m Dnu m m m R W m m m I 0 r. N6 mm 9 mm S w f .I 0.t' M 2 Urm m m .1 MN m m w 55 5 5 [i .1 rt 2 counter outputs and thenumber ofJohnson counter outputs.

PATENTED HAR23 I97! SHEET 1 OF 2 R m A L L C s O T T N w N E L L OOO OO/W V OO OOO y O OOOO o OOOO 66 23456 E 3 H 0OOO I J C OOO O J C OO O J CO O 0 J EBMBR ATTORNEY CLOCKING SYSTEM BACKGROUND OF THE INVENTION Thisinvention relates generally to digital systems, and more particularlyrelates to a system for producing a number of in dividually identifiableclock pulses which occur in a predetermined sequence.

In digital logic systems such as. for example, computers. dataprocessors and automated control systems, it is often necessary toutilize a sequence control having a number of individually identifiablepulses which occur in a predetermined sequencev Perhaps the mostapparent solution to this problem is to provide a ring counter havingthe desired number of outputs, although a binary counter with a suitablebinary-to-numerical decoder might also be used. However, theseapproaches require a relatively large number of circuit components andare not wholly satisfactory.

SUMMARY OF INVENTION CLAIMED A fist counter having a plurality ofoutputs for sequentially producing a pulse on each output, then after adelay period, repeating the sequence, and a second counter having aplurality of outputs for sequentially producing a pulse on each outputand then repeating the sequence, the second counter being clocked by thefirst counter during the delay period. More specifically, the firstcounter is preferably a ring counter including a delay stage, and thesecond counter is a Johnson counter which is clocked through a delaycircuit by the last output from the ring counter preceding the delayperiod.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic logic diagram ofa clocking system in accordance with the present invention;

FIG. 2 is a logic diagram illustrating the operation of the ring counterof the clocking system of FIG. 1;

FIG. 3 is a logic table illustrating the operation of the Johnsoncounter of the clocking system of FIG. 1;

FIG. 4 is a timing diagram illustrating the state of the outputs T,T ofthe Johnson counter during each cycle; and

FIG. is a timing diagram illustrating the operation of the clockingsystem of FIG. 1.

DESCRIPTION OF A PREFERRED EMBODIMENT Referring now to the drawings, aclocking system in accordance with the present invention is indicatedgenerally by the reference numeral 10 in FIG. 1. The clocking system 10is comprised of a ring counter indicated generally by the referencenumeral 12 having four binary stages RC,, RC RC and RC,. Each of thebinary stages may comprise a conventional J-K flip-flop having I and Kinputs and true and complement outputs T and C, respectively, asindicated. The J -K flip-flops assume a state after each clock pulsefrom an oscillator 14 that is dependent upon the state of the inputsprior to the clock pulse. If a logic 1 is applied to the J input and alogic 0 to the K input, the flip-flop will assume a logic l state withthe true output T at a logic 1 level. If the J input is a logic 0 andthe K input a logic 1, the flip-flop will assume a logic 0 state afterthe clock pulse with the true output a logic 0 level. The conditionswhen both J and K inputs are a logic I and when both J and K inputs area logic 0 are not used.

The binary stages RC,RC are connected with the true output T of stage RCconnected to the J input of stage RC the true output T of stage RCconnected to the J input of stage RC and the true output T of stage RCconnected to the J input of stage RC The true output T of each of thestages RC RC is also connected back to the K input of the stage so thatthe stage will automatically be set back to the logic 0 state on thefirst clock pulse after going to a logic 1 state. The complement outputsC of all four stages RC RC., are connected back to the inputs of an ANDgate 16, and the output of AND gate 16 is connected to the J input ofStage RC The true output T of stages RC RC are connected to the outputsP P.,, respectively, of the ring counter 12,

LII

The true output T of stage RC is connected through an invertingamplifier 18 to the clock inputs of each of the four stages JC,. JC JC;,and JC of a Johnson counter indicated generally by the reference numeral19. Johnson counters of the type disclosed herein are described in U.S.Patent No. 2,853,238 issued to R. R. Johnson on Sept. 23, 1958. Each ofthe stages JC JC may also comprise a conventional J-K flip-flop. Thetrue and complement outputs of stage JC, are connected to the J and Kinputs, respectively, of stage JC the true and complement outputs ofstage JC are connected to the J and K inputs, respectively, of stage JCand the true and complement outputs of stage JC are connected to the Jand K inputs, respectively, of stage JC,. However, the true andcomplement outputs of stage JC, are connected to the K and J inputs,respectively, of stage JC In addition, the complement outputs of stagesJC and JC, are connected to the inputs of a NAND gate 20 the output ofwhich is connected through an inverting amplifier 22 to the reset inputsof stages JC and J C;,. This is to prevent the counter from operating inthe illegal mode.

The true and complement outputs of stages JC -JC are connected to theinputs of a bank of NAND gates G G The output of each of the NAND gatesis connected to inverting amplifiers D -D having outputs T Trespectively. The inputs to gate G are taken from the complement outputsof stages JC and JC,. The inputs of gate G are taken from the trueoutput of stage JC and the complement output of stage JC The inputs ofgate G are taken from the true output of stage JC and the complementoutput of stage JC;,. The inputs of gate G are taken from the trueoutput of stage JC and the complement output of stage JC,, the inputs ofgate G are taken from the true output of stage JC, and the true outputof stage JC the inputs of gate G are taken from the complement output ofstage JC and the true output of stage JC the inputs to gate G are takenfrom the complement output of stage JC and the true output of stageJC;,, and the inputs of gate G are taken from the complement output ofstage JC and the true output of stage JC,.

OPERATION The operation of the ring counter 12 may best be understood byreferring to FIG. 2. Assume that after a clock pulse t from theoscillator 14, all of the stages RC RC are at a logic 0 state. The logic1 levels of the complement outputs will then satisfy the inputs of thegate 16 so that a logic I level will be applied to the J input of stageRC Then on the next clock pulse t the true output, and therefore outputP,, will go to a logic 1 level. The complement output of stage RC willgo to a logic 0 level so that the output of AND gate 16 will go to alogic 0 level. The logic 1 level of the true output of stage RC isapplied back to the K input of stage RC and to the J input of stage RCOn clock pulse t stage RC will complement back to a logic 0 state as aresult of the logic I level at the K input, and stage RC will complementto a logic lstate as a result of the logic I level at the J input sothat output P goes to a logic I level. The complement output of stage RCwill go to a logic 0 level so that the output of gate 16 will remain ata logic 0 level. The logic I level of the true output of stage RC isthen applied to the K input of stage RC and to the J input of stage RCOn clock pulse t stage RC complements back to a logic 0 state, and stageRC complements to a logic I state, with output P going to a logic Ilevel. The logic 0 level at the complement output of stage RC maintainsthe output of AND gate 16 at a logic 0 level. The logic l level of thetrue output of stage RC is fed back to the K input of stage RC and tothe J input of stage RC On clock pulse t stage RC complements back to alogic 0 state, and stage RC complements to a logic I state, thus raisingoutput P to the logic I level. The complement output C of stage RC goesto a logic 0 level to maintain the output of gate 16 at a logic 0 level.On clock pulse t stage RC goes to a logic 0 level. All four outputs P,-Pare then at a logic 0 level. The complement outputs C of all four stagesRC, -R(, are at a logic 1 level. the output of AND gate 16 is thereforeat a logic I level. Then on clock pulse t,,, stage RC, complements to alogic 1 state and the cycle is repeated.

The inverting amplifier 18 produces a clock pulse for the Johnsoncounter 19 only in response to each negative going transition of thetrue output T of stage RC, of the ring counter 12. When first set inoperation, the Johnson counter can assume an illegal mode of operation.However, in the illegal mode, stages JC, and JC, do assume a logic stateat the same time. At this time, stages JC and JC are immediately resetto the logic 0 state before the next clock pulse, at which time all fourstages will be in the logic 0 state. Then on the next four successiveclock pulses, stages JC,, JC JC, and JC, complement to the logic Istate, and then on the following four clock pulses, stages JC,, JC JC,and JC successively complement back to the logic 0 state. The cycle isthen repeated. As a result of the connections of the true and complementoutputs of the binary stages JC,JC, to the inputs of gates G,G outputsT,T,, go to a logic 1 level when the true outputs of the stages JC,JCare at the logic levels indicated in the truth table of FIG. 3. Thus,the outputs T,T,, successively go to a logic I in the sequenceillustrated in the timing diagram of FIG. 4, the clock pulses frominverter 18 being represented by dotted lines X,--X,,,.

The coincidence between the operation of the ring counter 12 and theJohnson counter 19 is illustrated in the timing diagram of FIG. 5. Thelogic levels of the four outputs P,P of the ring counter 12 areindicated by the time lines 3l34. Similarly, the logic levels of theeight outputs T,T,, are represented by the time lines 35-38. Assume thatprior to time t the stages RC,RC are in the logic 0 state and stage RC,is in the logic I state so that output P, of the ring counter 12 will beat a logic 1 level as represented by pulse 34a. Assume also that stagesJC,JC are in the logic 0 state and that stage JC is in the logic 1 stateso that only output T,, is at a logic 1 level. Then on clock pulse t P,will go to a logic 0 and all outputs P,-P, of the ring counter will beat a logic 0 level. As the output P, goes to a logic 0 level, inverter18 emits clock pulse X, which complements stage JC, to a logic 0 stateso that output T, will go to a logic 1 level as illustrated at 35a.However, some propagation delay results before the negative goingtransition of the true output of stage RC, of the ring counter appearsas a positive going transition at output T, of the Johnson counter. Thisis represented for simplicity as a delay occurring in inverter 18, whichindeed does produce some delay, but also occurs in the Johnson counter.The total delay may be approximately one-half the period of oscillator14. Thus, output T, goes positive after the occurrence of clock pulset,,, but before the occurrence of clock pulse t,. Then upon theoccurrence ofclock pulses t,, t t,, and t,, the outputs P,P,successively go to the logic I level as indicated by pulses 31a, 32a,33a and 3411, respectively. Then after the fifth clock pulse, thenegative going portion of pulse 34a produces a clock pulse X at theoutput of inverter 18. Clock pulse X increments the Johnson counter 19so that output T, goes to a logic 0 level at 35b and output T goes to alogic I level at 36a prior to the occurrence of clock pulse t and duringthis interval all of the outputs P,-P,, are at a logic 0 level. Thenoutputs P,-P, again successively rise to a logic I level on clock pulsest,,t as represented by the pulses 31b, 32b, 33b and 34b. Then as theoutput P, goes to a logic 0 level at the end of pulse 340, another clockpulse X is generated by inverter 18 which increments the Johnson counter19, causing output T to go to a logic 0 level as represented at 37a.This cycle is repeated for each of the eight outputs T,T

Any one of the outputs P,P, can be ANDed with any one of the outputsT,T,,, as represented by AND gate 40 in FIG. 1. The AND gate 40 willthen produce a logic 1 output only during period 01 between clock pulset, and clock pulse t Thus, four distinct pulse periods occur during eachof the eight counts of the Johnson counter 19, giving a total of 32sequential counts which can be individually identified. For example,periods 01-04 (see the bottom of FIG. 5) are defined by a logic 1 levelat output T, and outputs P,P,, respectively.

Periods 0508 are defined during the period when output T is at a logic Ilevel, periods 090l2 during the period outputs T is at a logic 1 level,etc. By changing the logic level of outputs T,T,, during the delayperiod when the four outputs P,- P., of the ring counter are at a logic0 level, the possibility of any spurious spikes being produced from thegate 40, or the other similar gates represented by gate 40 which may beused to identify one of the 32 periods, is eliminated.

Although a preferred embodiment of the invention has been described indetail, it is to be understood that various changes, substitutions andalterations can be made therein without departing from the spirit andscope of the invention as defined by the appended claims.

Iclaim:

1. The clocking system comprising a first counter having a plurality ofoutputs for sequentially producing a pulse on each output and after adelay count when the outputs from said first counter are zero repeatingthe sequence, said first counter comprising a plurality of synchronousbinary stages, means serially interconnecting the stages such that afterthe first stage complements to a logic 1 state, the succeeding stagessequentially complement, on successive clock pulses, from a logic 0state to a logic I state, means connecting an output of each stage to aninput of each stage for causing each stage to complement back to thelogic 0 state on the first clock pulse after going to the logic 1 state,delay means connecting an output of the last stage to an input of thefirst for complementing the first state to the logic 1 state on thefirst clock pulse after the last stage goes to the logic 0 state, asecond counter having a plurality of inputs and outputs for sequentiallyproducing a pulse on each output and then repeating the sequence, delaymeans connecting an output of the last stage of said first counter tothe clock inputs of said second counter such that the second counter isincremented after the last stage of the first counter goes to a logic 0state and before the first stage of the first counter goes to a logic 1state during the delay count of the first counter when the outputs fromsaid first counter are 0 whereby any one of the outputs of the firstcounter may be ANDed with any output of the second counter so that anyone of a total number of sequential periods equal to the product of thenumber of outputs of the first counter and the number of outputs of thesecond counter can be specifically identified without spurious spikesbeing produced in said total number of sequential periods.

2. The clocking system defined in claim 1 wherein the second counter iscomprised of a plurality of synchronous binary stages, means seriallyinterconnecting the binary stages such that after the first complementsto the logic 1 state, the remaining stages sequentially complement tothe logic l state on successive clock pulses, and means interconnectingthe outputs of the last stage to the inputs of the first stage forcausing the first stage to complement to the logic 0 state on the nextclock pulse after the last stage goes to the logic 1 state and tocomplement to the logic I state on the next clock pulse after the laststage goes to the logic 0 state, and logic gate means connected to theoutputs of the binary stages of the second counter including a number ofoutputs equal to twice the number of binary stages of the second counterfor sequentially producing a logic 1 level on each output on successiveclock pulses to the second counter and repeating the sequence.

1. The clocking system comprising a first counter having a plurality ofoutputs for sequentially producing a pulse on each output and after adelay count when the outputs from said first counter are zero repeatingthe sequence, said first counter comprising a plurality of synchronousbinary stages, means serially interconnecting the stages such that afterthe first stage complements to a logic 1 state, the succeeding stagessequentially complement, on successive clock pulses, from a logic 0state to a logic 1 state, means connecting an output of each stage to aninput of each stage for causing each stage to complement back to thelogic 0 state on the first clock pulse after going to the logic 1 state,delay means connecting an output of the last stage to an input of thefirst for complementing the first state to the logic 1 state on thefirst clock pulse after the last stage goes to the logic 0 state, asecond counter having a plurality of inputs and outputs for sequentiallyproducing a pulse on each output and then repeating the sequence, delaymeans connecting an output of the last stage of said first counter tothe clock inputs of said second counter such that the second counter isincremented after the last stage of the first counter goes to a logic 0state and before the first stage of the first counter goes to a logic 1state during the delay count of the first counter when the outputs fromsaid first counter are 0 whereby any one of the outputs of the firstcounter may be ANDed with any output of the second counter so that anyone of a total number of sequential periods equal to the product of thenumber of outputs of the first counter and the number of outputs of thesecond counter can be specifically identified without spurious spikesbeing produced in said total number of sequential periods.
 2. Theclocking system defined in claim 1 wherein the second counter iscomprised of a plurality of synchronous binary stages, means seriallyinterconnecting the binary stages such that after the first complementsto the logic 1 state, the remaining stages sequentially complement tothe logic 1 state on successive clock pulses, and means interconnectingthe outputs of the last stage to the inputs of the first stage forcausing the first stage to complement to the logic 0 state on the nextclock pulse after the last stage goes to the logic 1 state and tocomplement to the logic 1 state on the next clock pulse after the laststage goes to the logic 0 state, and logic gate means connected to theoutputs of the binary stages of the second counter including a number ofoutputs equal to twice the number of binary stages of the second counterfor sequentially producing a logic 1 level on each output on successiveclock pulses to the second counter and repeating the sequence.